1. Field of the Invention
The present Invention relates to a metal(M)-insulator(I)semiconductor(s) device generally known as a MIS semiconductor device (also known as an insulated-gate semiconductor device). Such MIS semiconductor devices include, for example, MOS transistors, thin-film transistors, and the like.
2. Description of the Prior Art
In the prior art, MIS semiconductor devices have been fabricated using self-alignment techniques. According to such techniques, a gate electrode is formed on a semiconductor substrate or a semiconductor film with a gate insulating film interposed therebetween, and using the gate electrode as a mask, impurities are introduced into the semiconductor substrate or the semiconductor film. Thermal diffusion, ion implantation, plasma doping, and laser doping are typical methods of introducing impurities. With self-alignment techniques, the edges of the impurity doped regions (source and drain) can be substantially aligned with the edges of the gate electrode, eliminating the overlap between the gate electrode and the doped regions (that could give rise to the formation of parasitic capacitances) as well as the offset that causes separation between the gate electrode and the doped regions (that could reduce effective mobility).
The prior art process, however, has had the problem that the spatial carrier concentration gradient between the doped regions and their adjacent active region (channel forming region) formed below the gate electrode is too steep, thus causing an extremely high electric field and increasing, in particular, the leakage current (OFF current) when a reverse bias is applied to the gate electrode.
To address such a problem, the present inventor et al. have found that an improvement can be made by slightly offsetting the gate electrode with respect to the doped regions, and also that an offset of 300 nm or less can be obtained with good reproducibility by forming the gate electrode from an anodizable material and by introducing impurities by using the resulting anodic oxide film also as a mask.
Furthermore, in the case of ion implantation, plasma doping and other methods that involve driving high-velocity ions into a semiconductor substrate or a semiconductor film to introduce impurities, the crystallinity of the semiconductor substrate or film needs to be improved (activation) since the crystallinity of the structure where ions are driven is damaged by the penetrating ions. In the prior art, it has been practiced to improve the crystallinity by thermal means using temperatures of 600xc2x0 C. or higher, but according to the recent trend, lower process temperatures are demanded. In this view, the present inventor et al. have also shown that the activation can be accomplished by using laser or equivalent high-intensity light and that such activation has significant advantages for mass production.
FIG. 2 shows a fabrication process sequence for a thin-film transistor based on the above concept. First, a base insulating film 202 is deposited over a substrate 210, and a crystalline semiconductor region 203 is formed in the shape as an island, over which an insulating film 204 that acts as a gate insulating film is formed. Then, a gate connection 205 is formed using an anodizable material. (FIG. 2(A))
Next, the gate connection is anodized to form an anodic oxide film 206 to a thickness of 300 nm or less, preferably 250 nm or less, on the surface of the gate connection. Using this anodic oxide as a mask, impurities (for example, phosphorous (P)) are driven by using a method such as ion implantation or ion doping to form impurity doped regions 207. (FIG. 2(B))
Thereafter, high-intensity light such as laser light is radiated from above to activate the regions where the impurities have been introduced. (FIG. 2(C))
Finally, an inter-layer insulator 208 is deposited, contact holes are opened over the doped regions, and electrodes 209 are formed for connection to the doped regions, thus completing the fabrication of the thin-film transistor. (FIG. 2(D))
However, it has been found that in the above-described process, the boundaries (indicated by X in FIG. 2(C)) between the doped regions and the active region (the semiconductor region directly below the gate and flanked by the doped regions) are unstable, and that the reliability decreases due to increased leakage current, etc. after use for long periods of time. That is, as can be seen from the process, the crystallinity of the active region remains substantially unchanged throughout the process; on the other hand, the doped regions adjacent to the active region initially have the same crystallinity as that of the active region but their crystallinity is damaged during the process of impurity introduction. The doped regions are repaired in the subsequent laser radiation step, but it is difficult to restore the original crystallinity. Furthermore, it has been found that in particular, the portions of the doped regions that contact the active region cannot be activated sufficiently as such portions tend to remain unexposed to laser radiation. This results in discontinuity in the crystallinity between the doped regions and the active region, tending to cause trapping states, etc. In particular, when impurities are introduced using a method that involves driving high-velocity ions, the impurity ions are caused to scatter and penetrate into regions below the gate electrode, so that the crystallinity of these regions is damaged. It has not been possible to activate such regions lying below the gate electrode by laser or other light since they are in the shadow of the gate electrode.
One way to solve this problem is to radiate laser or other light from the reverse side to activate these regions. In this method, the boundaries between the active region and the doped regions can be activated sufficiently since the light is not blocked by the gate connection. This method, however, requires that the substrate material be transparent to light, and as a matter of course, cannot be employed when a silicon wafer or the like is used as the substrate. Furthermore, most glass materials do not easily transmit ultraviolet light of wavelength below 300 nm; therefore, KrF excimer lasers (wavelength 248 nm), for example, that achieve excellent mass productivity cannot be used.
In view of the above problems, it is an object of the present invention to provide a MIS semiconductor device, such as a MOS transistor and thin-film transistor, wherein device reliability is enhanced by achieving continuity in the crystallinity between the active and doped regions.
In the present invention, provisions are made so that when light energy emitted from a high-intensity light source such as a laser or a flash lamp is projected onto impurity doped regions from above for activation thereof, not only the doped regions but also a part of an active region adjacent thereto, in particular, the boundaries between the active region and the doped regions, are exposed to the light energy. To achieve the purpose, a portion of a material forming a gate electrode is removed.
According to a first mode of the invention, the process comprises: a step in which a material that acts as a mask for the formation of doped regions is formed over a crystalline semiconductor substrate or semiconductor film, and then, using this material as the mask, impurities are introduced into the semiconductor substrate or semiconductor film; a step in which the masking material is removed so that light energy can be projected onto both the doped and active regions, and in this condition, the light energy is projected for activation; and a step in which a gate electrode (gate connection) is formed on the active region.
When this process is employed, if an offset region is to be formed, the mask pattern for the formation of the doped regions needs to made larger in width than the gate electrode pattern. If the gate electrode pattern were made larger in width than the mask pattern for impurity injection, the resulting gate electrode would overlap the doped regions.
Furthermore, it is difficult to precisely place masks at the same place in different steps when different photo masks are used. In particular, it is almost impossible to realize the offset condition of 1 xcexcm or less, as required by the invention, in mass production. On the other hand, overlaying by using the same photo mask is relatively easy. Suppose, for example, that by using a certain photo mask, a connection pattern is formed, and then by using this pattern as a mask, impurity doped regions are formed, followed by the removal of the connection. When this same photo mask is used to form a connection subsequently, almost no offset is produced. However, by anodizing the surface of the connection after that, the conductive surface of the connection recedes and the desired offset is achieved.
On the other hand, if the first formed connection is anodized, the surface of the resulting anodic oxide advances; if doped regions are formed using this anodized connection as a mask, the doped regions are formed outwardly of the initially formed connection pattern. Then, by anodizing the second connection, the conductive surface of the connection recedes and the offset is increased.
Thus, by forming the gate electrode from an anodizable material and then anodizing the gate electrode, the desired offset can be obtained with relative ease. It will be recognized that the resulting anodic oxide also serves to prevent shorting between layers. It will also be appreciated that the gate electrode (connection) may be covered with an inter-layer insulator or the like, in addition to the anodic oxide, to reduce the capacitive coupling with upper connections.
According to a second mode of the invention, the process comprises: a step in which an insulating film that acts as a gate insulating film is formed on a crystalline semiconductor substrate or semiconductor film, and then by using the insulating film as a mask, impurities are introduced in self-aligned fashion into the semiconductor substrate or semiconductor film; and a step in which ends of a gate electrode are selectively etched so that the gate electrode is offset with respect to impurity doped regions and so that light energy can be projected onto the boundaries between the doped and active regions, and in this condition, the light energy is projected for activation.
Preferably, the gate electrode is formed from an anodizable material, and after exposure to the light energy, the gate electrode is anodized to cover its surface with a high-resistance anodic oxide, which is further covered with an inter-layer insulator or the like to reduce the capacitive coupling with upper connections.
According to a third mode of the invention, the process comprises: a step in which an insulating film that acts as a gate insulating film is formed on a crystalline semiconductor substrate or semiconductor film, followed by the formation of a gate connection (gate electrode) using an appropriate material, and then by using the gate connection as an electrode, the surface of the electrode is electrochemically coated with a conductive material or the like by an electrochemical reaction (e.g., electroplating); a step in which impurities are introduced in self-aligned fashion into the semiconductor substrate or semiconductor film by using the thus processed gate electrode region (the gate electrode and the conductive material deposited on its surface) as a mask; and a step in which part or whole of the previously deposited material is removed so that light energy can be projected onto the boundaries between the doped and active regions, and in this condition, the light energy is projected for activation.
Preferably, the gate electrode is formed from an anodizable material, and after exposure to the light energy, the gate electrode is anodized to cover its surface with a high-resistance anodic oxide, which is further covered with an inter-layer insulator or the like to reduce the capacitive coupling with upper connections.
Anodizable materials preferable for use in the present invention include aluminum, titanium, tantalum, silicon, tungsten, and molybdenum. These materials may be used singly or in alloy form to form a gate electrode of a single layer or multilayer structure. It will be recognized that a minute amount of other elements may be added to the above materials. For anodic oxidation, a wet process is commonly employed in which oxidation is carried out in an electrolyte, but it will be appreciated that a known plasma anodic oxidation method (oxidation in a reduced-pressure plasma atmosphere) may be employed. It will be further appreciated that the oxidation process is not limited to anodic oxidation but that other suitable oxidation methods may be used.
Sources for light energy suitable for use in the present invention include: excimer lasers such as KrF lasers (wavelength 248 nm), XeCl lasers (308 nm), ArF lasers (193 nm), XeF lasers (353 nm), etc.; Nd:YAG lasers (1064 nm) and its second, third, and fourth harmonics; coherent light sources such as carbon dioxide gas lasers, argon ion lasers, copper vapor lasers, etc.; and incoherent light sources such as xenon flash lamps, krypton arc lamps, etc.
The MIS semiconductor device fabricated by the above process is characterized in that, when viewed from the top, the junctions of the doped regions (source and drain) and the gate electrode region (including the gate electrode and its associated anodic oxide) are essentially the same in shape (similar form), and that the gate electrode (defined by its conductive surface and excluding its associated anodic oxide) is offset with respect to the doped regions.
When the gate electrode has no oxide, such as anodic oxide, formed thereon, there is no oxide formed around the gate electrode, and the gate electrode is offset with respect to the doped regions, the width of the offset preferably being 0.1 to 0.5 xcexcm.
In the present invention, it is also possible to control the thicknesses of individual oxides such as anodic oxides formed on the same substrate by adjusting, for example, the applied voltage for each connection. In this case, the thickness of the oxide formed part of the gate electrode region and the thickness of the oxide forming part of a capacitor (or a portion at an intersection between connections) may be set independently of each other to appropriate values that suit their respective purposes.